Issued Patents 2003
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651144 | Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state | Rahul Razdan, Richard E. Kessler | 2003-11-18 |
| 6651161 | Store load forward predictor untraining | Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad | 2003-11-18 |
| 6647490 | Training line predictor for branch targets | Puneet Sharma, Keith R. Schakel, Francis Matus | 2003-11-11 |
| 6636959 | Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition | Puneet Sharma, Keith R. Schakel, Francis Matus | 2003-10-21 |
| 6633936 | Adaptive retry mechanism | Chun Ning, Kwong-Tak Chui, Mark D. Hayter | 2003-10-14 |
| 6631401 | Flexible probe/probe response routing for maintaining coherency | Dale E. Gulick | 2003-10-07 |
| 6625685 | Memory controller with programmable configuration | James Y. Cho, Mark D. Hayter | 2003-09-23 |
| 6622237 | Store to load forward predictor training using delta tag | Thomas S. Green, Wei-Han Lien, Ramsey W. Haddad, Keith R. Schakel | 2003-09-16 |
| 6622235 | Scheduler which retries load/store hit situations | Ramsey W. Haddad, Stephan G. Meier | 2003-09-16 |
| 6564315 | Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction | Ramsey W. Haddad, Stephan G. Meier | 2003-05-13 |
| 6560694 | Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode | Kevin J. McGrath | 2003-05-06 |
| 6557048 | Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof | Derrick R. Meyer, Dale E. Gulick, Larry D. Hewitt | 2003-04-29 |
| 6553430 | Computer system implementing flush operation | — | 2003-04-22 |
| 6546478 | Line predictor entry with location pointers and control information for corresponding instructions in a cache line | Puneet Sharma, Keith R. Schakel, Francis Matus | 2003-04-08 |
| 6542984 | Scheduler capable of issuing and reissuing dependency chains | Ramsey W. Haddad, Stephan G. Meier | 2003-04-01 |
| 6529999 | Computer system implementing system and method for ordering write operations and maintaining memory coherency | Derrick R. Meyer | 2003-03-04 |