JR

Jaroslav Raszka

VL Virage Logic: 2 patents #2 of 10Top 20%
📍 San Jose, CA: #402 of 2,494 inventorsTop 20%
🗺 California: #3,859 of 26,763 inventorsTop 15%
Overall (2002): #60,231 of 266,432Top 25%
2
Patents 2002

Issued Patents 2002

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6473356 Low power read circuitry for a memory circuit based on charge redistribution between bitlines and sense amplifier 2002-10-29
6392957 Fast read/write cycle memory device having a self-timed read/write control circuit Alexander Shubat, Adam Kablanian, Richard S. Roy 2002-05-21