CT

Chong Guan Tan

VD Verisity Design: 1 patents #1 of 5Top 20%
📍 Saratoga, CA: #159 of 356 inventorsTop 45%
🗺 California: #8,284 of 26,763 inventorsTop 35%
Overall (2002): #240,095 of 266,432Top 95%
1
Patents 2002

Issued Patents 2002

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6487704 System and method for identifying finite state machines and verifying circuit designs Michael T. McNamara, Chiahon Chien, David Massey 2002-11-26