Issued Patents 2002
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6468849 | Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology | Taylor R. Efland, Chin-Yu Tsai | 2002-10-22 |
| 6413824 | METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS | Amitava Chatterjee, Mark S. Rodder, Taylor R. Efland, Chin-Yu Tsai, James R. Hellums | 2002-07-02 |