SA

Shirish A. Altekar

Lsi Logic: 2 patents #56 of 388Top 15%
📍 Palo Alto, CA: #173 of 925 inventorsTop 20%
🗺 California: #3,859 of 26,763 inventorsTop 15%
Overall (2002): #42,310 of 266,432Top 20%
2
Patents 2002

Issued Patents 2002

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6484286 Error signal calculation from a Viterbi output Paul K. Lai, Kwok W. Yeung 2002-11-19
6476737 Rate 64/65 (d=0, G=11/I=10) run length limited modulation code Joseph Caroselli, Charles E. MacDonald 2002-11-05