Issued Patents 2002
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501328 | Method for reducing peak to peak jitter in a dual-loop delay locked loop | Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi | 2002-12-31 |
| 6495926 | 60 degree bump placement layout for an integrated circuit power grid | Sudhakar Bobba, Dean Liu | 2002-12-17 |
| 6483341 | CMOS-microprocessor chip and package anti-resonance apparatus | Claude Gauthier, Richard L. Wheeler, Brian Amick | 2002-11-19 |
| 6476663 | Method for reducing supply noise near an on-die thermal sensor | Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi | 2002-11-05 |
| 6473883 | Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid | Sudhakar Bobba | 2002-10-29 |
| 6456107 | CMOS-microprocessor chip and package anti-resonance method | Claude Gauthier, Richard L. Wheeler, Brian Amick | 2002-09-24 |
| 6441640 | CMOS-microprocessor chip and package anti-resonance pass-band shunt apparatus | Claude Gauthier, Brian Amick, Richard L. Wheeler | 2002-08-27 |