Issued Patents 2002
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6466509 | Semiconductor memory device having a column select line transmitting a column select signal | Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa +3 more | 2002-10-15 |
| 6463098 | Data transfer circuit transferring 2-bit data through 4 data lines | Masatoshi Ishikawa | 2002-10-08 |
| 6452976 | Data transfer circuit with reduced current consumption | Masatoshi Ishikawa | 2002-09-17 |
| 6445633 | Read amplifier circuit for high-speed reading and semiconductor memory device employing the read amplifier circuit | Mitsue Takahashi | 2002-09-03 |
| 6430091 | Semiconductor memory device having reduced current consumption at internal boosted potential | — | 2002-08-06 |
| 6411560 | Semiconductor memory device capable of reducing leakage current flowing into substrate | Shigeki Tomishima, Mitsutaka Niiro, Masanao Maruta, Hiroshi Kato, Masatoshi Ishikawa +3 more | 2002-06-25 |
| 6400632 | Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall | Hideto Hidaka, Tsukasa Ooishi, Shigeki Tomishima, Hiroshi Kato | 2002-06-04 |
| 6385125 | Synchronous semiconductor integrated circuit device capable of test time reduction | Tsukasa Ooishi, Shigeki Tomishima, Yutaka Komai | 2002-05-07 |
| 6384674 | Semiconductor device having hierarchical power supply line structure improved in operating speed | Tsukasa Ooishi, Shigeki Tomishima, Masatoshi Ishikawa, Hideto Hidaka, Takaharu Tsuji | 2002-05-07 |
| 6381167 | Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof | Tsukasa Ooishi | 2002-04-30 |