Issued Patents 2002
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6466507 | DRAM with intermediate storage cache and separate read and write I/O | — | 2002-10-15 |
| 6452867 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2002-09-17 |
| 6449679 | RAM controller interface device for RAM compatibility (memory translator hub) | — | 2002-09-10 |
| 6445636 | Method and system for hiding refreshes in a dynamic random access memory | Brent Keeth, Brian M. Shirley, Charles H. Dennison | 2002-09-03 |
| 6442644 | Memory system having synchronous-link DRAM (SLDRAM) devices and controller | David Gustavson, David V. James, Hans A. Wiggers, Peter B. Gillingham, Cormac Michael O'Connell +9 more | 2002-08-27 |
| 6418495 | Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus | — | 2002-07-09 |
| 6415340 | Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths | Terry R. Lee | 2002-07-02 |
| 6405280 | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence | — | 2002-06-11 |
| 6374360 | Method and apparatus for bit-to-bit timing correction of a high speed memory bus | Brent Keeth, Terry R. Lee, Troy A. Manning | 2002-04-16 |
| 6356506 | Full page increment/decrement burst for DDR SDRAM/SGRAM | — | 2002-03-12 |