Issued Patents 2002
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6496422 | Memory structure utilizing four transistor load less memory cells and a bias generator | — | 2002-12-17 |
| 6388933 | Method of controlling the conduction of the access transistors of a load less, four transistor memory cell | — | 2002-05-14 |
| 6373756 | Memory structure utilizing four transistor load less memory cells and a bias generator | — | 2002-04-16 |
| 6353521 | Device and method for protecting an integrated circuit during an ESD event | Dean D. Gans | 2002-03-05 |
| 6337813 | Method of regulating a voltage difference between a word line and a digit line of a load less, four transistor memory cell | — | 2002-01-08 |