Issued Patents 2002
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6498377 | SONOS component having high dielectric property | Hung-Sui Lin, Nian-Kai Zous, Han-Chao Lai | 2002-12-24 |
| 6492235 | Method for forming extension by using double etch spacer | Han-Chao Lai, Hung-Sui Lin | 2002-12-10 |
| 6482709 | Manufacturing process of a MOS transistor | Han-Chao Lai, Hung-Sui Lin | 2002-11-19 |
| 6482706 | Method to scale down device dimension using spacer to confine buried drain implant | Yen-Hung Yeh, Tso-Hung Fan, Mu-Yi Liu, Kwang-Yang Chan | 2002-11-19 |
| 6465849 | CMOS structure having dynamic threshold voltage | Yao-Wen Chang | 2002-10-15 |
| 6458642 | Method of fabricating a sonos device | Yen-Hung Yeh, Tso-Hung Fan, Mu-Yi Liu, Kwang-Yang Chan | 2002-10-01 |
| 6458643 | Method of fabricating a MOS device with an ultra-shallow junction | Han-Chao Lai, Hung-Sui Lin | 2002-10-01 |
| 6455376 | Method of fabricating flash memory with shallow and deep junctions | Tso-Hung Fan, Wen-Jer Tsai | 2002-09-24 |
| 6455388 | Method of manufacturing metal-oxide semiconductor transistor | Han-Chao Lai, Hung-Sui Lin | 2002-09-24 |
| 6455898 | Electrostatic discharge input protection for reducing input resistance | Meng-Hwang Liu, Mam-Tsung Wang | 2002-09-24 |
| 6448142 | Method for fabricating a metal oxide semiconductor transistor | Han-Chao Lai, Hung-Sui Lin | 2002-09-10 |
| 6444523 | Method for fabricating a memory device with a floating gate | Tso-Hung Fan, Wen-Jer Tsai, Samuel C. Pan | 2002-09-03 |
| 6432782 | 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate | Hsing Lan Lung, Mam-Tsung Wang | 2002-08-13 |
| 6410963 | Electrostatic discharge protection circuits with latch-up prevention function | Chen-Shang Lai, Meng-Huang Liu, Shin Su | 2002-06-25 |