Issued Patents 2002
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6463572 | IC timing analysis with known false paths | Ivan Pavisic, Aiguo Lu | 2002-10-08 |
| 6453453 | Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes | Alexander E. Andreev, Anatoli Bolotov | 2002-09-17 |
| 6412102 | Wire routing optimization | Alexander E. Andreev, Ivan Pavisic | 2002-06-25 |