Issued Patents 2002
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6483754 | Self-time scheme to reduce cycle time for memories | — | 2002-11-19 |
| 6438046 | System and method for providing row redundancy with no timing penalty for built-in-self-repair (BISR) in high density memories | — | 2002-08-20 |
| 6404700 | Low power high density asynchronous memory architecture | — | 2002-06-11 |
| 6370078 | Way to compensate the effect of coupling between bitlines in a multi-port memories | Thomas R. Wik | 2002-04-09 |
| 6366508 | Integrated circuit memory having column redundancy with no timing penalty | Jerry K. Tanaka | 2002-04-02 |
| 6341092 | Designing memory for testability to support scan capability in an asic design | — | 2002-01-22 |