Issued Patents 2002
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6502222 | Method of clock buffer partitioning to minimize clock skew for an integrated circuit design | — | 2002-12-31 |
| 6496967 | Method of datapath cell placement for an integrated circuit | Qiong Yu | 2002-12-17 |
| 6480994 | Balanced clock placement for integrated circuits containing megacells | Rajiv Kapur | 2002-11-12 |
| 6449760 | Pin placement method for integrated circuits | Charutosh Dixit, Soon-lin Yeap | 2002-09-10 |
| 6442737 | Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees | Ruben Molina | 2002-08-27 |