Issued Patents 2002
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6487142 | Synchronous dynamic random access memory | — | 2002-11-26 |
| 6484246 | High-speed random access semiconductor memory device | Kenji Tsuchida, Hitoshi Kuyama | 2002-11-19 |
| 6480423 | High-speed cycle clock-synchronous memory device | Kenji Tsuchida, Hitoshi Kuyama | 2002-11-12 |
| 6473865 | Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal | Masahiro Kamoshida, Tsuneaki Fuse, Yukihito Oowaki | 2002-10-29 |
| 6469951 | Semiconductor memory having an overlaid bus structure | — | 2002-10-22 |
| 6449212 | Analog synchronization circuit for synchronizing external and internal clock signals | Hironobu Akita, Katsuaki Isobe | 2002-09-10 |
| 6449727 | High-speed data transfer synchronizing system and method | — | 2002-09-10 |
| 6442088 | Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory | Kenji Tsuchida | 2002-08-27 |
| 6430101 | Fuse circuit using anti-fuse and method for searching for failed address in semiconductor memory | — | 2002-08-06 |
| 6426912 | Test circuit for testing semiconductor memory | — | 2002-07-30 |
| 6396765 | Semiconductor memory having an overlaid bus structure | — | 2002-05-28 |
| 6393080 | Apparatus comprising clock control circuit and device using internal clock signal synchronized to external clock signal | Masahiro Kamoshida, Tsuneaki Fuse, Yukihito Oowaki | 2002-05-21 |
| 6389521 | Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access memory | — | 2002-05-14 |
| 6388484 | Clock control circuit | Masahiro Kamoshida, Tsuneaki Fuse, Yukihito Oowaki | 2002-05-14 |
| 6377503 | Synchronous dynamic random access memory | — | 2002-04-23 |
| 6373785 | Semiconductor memory device | Shozo Saito, Kaoru Tokushige | 2002-04-16 |
| 6363465 | Synchronous data transfer system and method with successive stage control allowing two more stages to simultaneous transfer | — | 2002-03-26 |
| 6337834 | Synchronous signal generation circuit | Katsuaki Isobe, Hironobu Akita, Satoshi Eto | 2002-01-08 |
| 6335904 | Semiconductor memory system, and access control method for semiconductor memory and semiconductor memory | Kenji Tsuchida | 2002-01-01 |