Issued Patents 2002
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6449712 | Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions | Naohiko Irie, Chih-Jui Peng, Sebastian Haviuj Ziesler, Jackie Andrew Freeman, Sivaram Krishnan | 2002-09-10 |
| 6397296 | Two-level instruction cache for embedded processors | — | 2002-05-28 |
| 6393523 | Mechanism for invalidating instruction cache blocks in a pipeline processor | Chih-Jui Peng, Margaret Rose Gearty, Naohiko Irie | 2002-05-21 |
| 6389531 | Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency | Naohiko Irle | 2002-05-14 |
| 6374348 | Prioritized pre-fetch/preload mechanism for loading and speculative preloading of candidate branch target instruction | Naohiko Irie | 2002-04-16 |