Issued Patents 2002
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6449694 | Low power cache operation through the use of partial tag comparison | Richard J. Burgess, Jr., Jay B. Miller | 2002-09-10 |
| 6434736 | Location based timing scheme in memory design | Richard J. Burgess, Jr., Jay B. Miller | 2002-08-13 |