WG

Walter J. Ghijsen

CS Cadence Design Systems: 1 patents #6 of 34Top 20%
📍 San Jose, CA: #851 of 2,494 inventorsTop 35%
🗺 California: #8,284 of 26,763 inventorsTop 35%
Overall (2002): #94,432 of 266,432Top 40%
1
Patents 2002

Issued Patents 2002

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6381563 System and method for simulating circuits using inline subcircuits Donald J. O'Riordan, Kenneth S. Kundert 2002-04-30