Issued Patents 2002
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6493862 | Method for compressing an FPGA bitsream | Jeffrey V. Lindholm | 2002-12-10 |
| 6472909 | Clock routing circuit with fast glitchless switching | — | 2002-10-29 |
| 6448809 | FPGA with a plurality of input reference voltage levels | F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli | 2002-09-10 |
| 6448808 | Interconnect structure for a programmable logic device | Kamal Chaudhary, Trevor J. Bauer | 2002-09-10 |
| 6445209 | FPGA lookup table with NOR gate write decoder and high speed read decoder | Trevor J. Bauer, Richard A. Carberry | 2002-09-03 |
| 6429698 | Clock multiplexer circuit with glitchless switching | — | 2002-08-06 |
| 6427156 | Configurable logic block with AND gate for efficient multiplication in FPGAS | Kenneth D. Chapman | 2002-07-30 |
| 6396303 | Expandable interconnect structure for FPGAS | — | 2002-05-28 |
| 6373779 | Block RAM having multiple configurable write modes for use in a field programmable gate array | Raymond C. Pang | 2002-04-16 |
| 6373279 | FPGA lookup table with dual ended writes for ram and shift register modes | Trevor J. Bauer, Richard A. Carberry | 2002-04-16 |
| 6362650 | Method and apparatus for incorporating a multiplier into an FPGA | Bernard J. New | 2002-03-26 |
| 6362648 | Multiplexer for implementing logic functions in a programmable logic device | Bernard J. New, Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, Roman Iwanczuk | 2002-03-26 |
| 6353341 | Method and apparatus for discriminating against signal interference | Austin H. Lesea, Peter H. Alfke, Jennifer Wong | 2002-03-05 |
| 6346825 | Block RAM with configurable data width and parity for use in a field programmable gate array | Raymond C. Pang, Trevor J. Bauer | 2002-02-12 |